1. Field of the Invention
The present invention relates to a filter for removing ghost signals or multipath signals from, for example, a received video signal, and more particularly, to an input-weighted transversal filter which performs filtering operations on digital signals, such as video signals, audio signals, etc., in real time.
2. Description of the Related Art
In general, a transversal filter adapted to remove ghosts usually requires 640 taps. The transversal filter is composed of a plurality of integrated-circuit chips. Thus, the number of integrated circuits used for the transversal filter can be decreased by increasing the number of taps per chip.
Coefficient multipliers which multiply a time-series input signal and predetermined coefficients form a large proportion of a transversal filter. Each of the coefficient multipliers is composed mainly of a multiplier. Even if the number of taps remain unchanged, therefore, by operating the coefficient multipliers on a time-division basis, it becomes possible to decrease the number of multipliers and reduce the circuit scale thereof in the transversal filter.
FIG. 6 illustrates a conventional transversal filter, and FIGS. 7A and 7B are its timing chart. This filter circuit illustrates the case where the number of taps is six and the number of coefficients to be time-division multiplexed is two.
In the case of ghost removal, an input signal is sampled at regular intervals T = about 70 nsec. The circuit operates coefficient multipliers on a time-division basis and switches coefficients by which sampled signals are multiplied twice during the interval T.
To an input terminal 1 is applied an input signal a={X(i)} which has been sampled every T. The input signal a is then applied to coefficient multipliers 10, 11, 12. The input signal has a period of T and varies as represented by EQU X(i-5), X(i-4), X(i-3), X(i-2), (1)
Each of selectors 13, 14 and 15 is supplied with two of coefficients C0 to C5. The two coefficients are selectively supplied to each of coefficient multipliers 10, 11 and 12 by a select signal S. For example, for the multiplier 10, the coefficient C0 is selected by the selector 13 when the select signal is a 1, while the coefficient C1 is selected when the select signal is a 0. In the mutiplier 10, therefore, the selectively applied coefficients and the input signal a={X(i)} are multiplied in sequence and the results of the multiplication are output as follows: EQU C0.multidot.X(i-5), C1.multidot.X(i-5), C0.multidot.X(i-4), C0.multidot.X (i-4), C0.multidot.X(i-3), (2)
The outputs d, c and b of the multipliers 10, 11 and 12 are applied to adders 16, 17 and 18, respectively. Delay elements 19 to 22 and 23 to 26 are connected in cascade between the adders 16 and 17 and between the adders 17 and 18, thereby constituting a pipeline adder. Each of the delay elements is arranged to introduce a time delay of T/2. Furthermore, delay elements 27 and 28 are connected in cascade between an input terminal 2 and the adder 18. To the input terminal 2 is applied an output signal of the preceding filter stage which is not shown.
Outputs of the multipliers 10 to 12 are added in the adders 16 to 18 and delayed by the delay elements 19 to 22 and 23 to 26 to be output from the adder 16 as data with a period of T/2. The output data alternates, as indicated at e in FIGS. 7A and 7B, between the sum .SIGMA.E of outputs of even-numbered taps assigned coefficients C0, C2 and C4 and the sum .SIGMA.O of outputs of odd-numbered taps assigned coefficients C1, C3 and C5 every T/2. The output data is further delayed by delay elements 29 and 30 and then output from an output terminal 3 as cascade data. The cascade data has a period of T/2= about 35 nsec. Interfacing between transversal filter stages connected in cascade is performed in this interval of about 35 nsec.
Data required finally in a transversal filter having six taps is represented by ##EQU1## For this reason, as shown in FIG. 6, the transversal filter requires at its final stage a demultiplexer circuit 33 constructed from delay elements 29, 30, an adder 31 and a delay element 32.
The output e of the adder 16 of FIG. 6 alternates, as described, between the sum .SIGMA.E of outputs of even-numbered taps and the sum .SIGMA.O of outputs of odd-numbered taps every T/2. Thus, by delaying one of the sums by T/2 with respect to the other in the delay element 30 and adding the input and output of the delay element together in the adder 31, such data as indicated at f in FIGS. 7A and 7B will result. Of such data, each of data pieces which are indicated by oblique lines represents EQU C1.multidot.X(i-1)+C3.multidot.X(i-3)+C5.multidot.X(i-5) +C0.multidot.(Xi)+C2.multidot.X(i-2)+C4.multidot.X(i-4),
which corresponds to the data expressed by equation (3). Thus, by holding each data piece indicated by oblique lines for the interval T by the delay element 32, output data of the transversal filter proper, which has recovered the period T corresponding to the sampling frequency, can be obtained.
FIG. 8 illustrates a cascade of transversal filter stages TF1, TF2, . . . , TFn each constructed as described above. Such a configuration allows the total number of taps to be increased.
As described above, however, data transmitted to the succeeding filter stage as cascade data has a period of T/2= about 35 nsec, and the interfacing of transversal filters will also be performed with this period. This period is very short. Therefore, when there are variations in manufacturing processes for integrating the transversal filter into chips, it will become difficult to interface a preceding stage with a succeeding stage with this period.
In addition, two output terminals are required: an output terminal 3 for connection to the succeeding transversal filter stage and an output terminal 4 for outputting demultiplexed data at the final stage. Thus, the transversal filter will require twice as many pins as output bits. As a countermeasure for this, output data may be switched by means of a selector to decrease the number of pins. In this case, however, an additional select signal for controlling the selector will be required and moreover an amount of hardware will be increased due to the provision of the selector. Thus, the switching of output data is not advantageous.